Trustworthy Computing Platforms and Devices
Cross Cutting Thrusts
Threat Analysis and Modeling
Diana Marculescu is a Professor of Electrical and Computer Engineering at Carnegie Mellon University. For the past two decades, she has done research in energy- and reliability-aware computing, and more recently, in CAD for non-silicon applications, including computational biology and sustainability. Diana received her Dipl. Ing. degree in Computer Science from "Politehnica" University of Bucharest, Romania in 1991, her Ph.D. in Computer Engineering from University of Southern California in 1998, and held visiting positions at Technical University Munich, University Joseph Fourier, and CEA-LETI. She is the recipient of a National Science Foundation Faculty Career Award (2000-2004), an ACM-SIGDA Technical Leadership Award (2003), the Carnegie Institute of Technology George Tallman Ladd Research Award (2004), an ACM-SIGDA Distinguished Service Award (2010), and several best paper awards. Diana is an IEEE Fellow and an ACM Distinguished Scientist and was an IEEE-Circuits and Systems Society Distinguished Lecturer (2004-2005) and the Chair of the ACM Special Interest Group on Design Automation (2005-2009). She was recently selected as an ELATE Fellow (2013-2014) and is the recipient of an Australian Research Council Future Fellowship (2013-2017) and the Marie R. Pistilli Women in EDA Achievement Award (2014). . Her research interests include energy-, reliability-, and variability-aware computing and CAD for non-silicon applications.
Ph.D. in Computer Engineering, University of Southern California, August 1998
M.S. in Computer Science, "Politehnica" University of Bucharest, Romania, June 1991
Research Area: Trustworthy Computing Platforms and Devices
Cross Cutting Thrusts: Threat Analysis and Modeling
Researcher: Diana MarculescuCross Cutting Thrusts: Cryptography
Researcher: Diana MarculescuResearcher: Diana Marculescu
"SLIC: Statistical Learning in Chip". R. D. Blanton, X. Li, K. W. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider, and D. E. Thomas, ISIC: International Symposium on Integrated Circuits, 2014.
"Energy-Efficient VFI-Partitioned Multicore Design Using Wireless NoC Architectures," R. Kim, G. Liu, P. Wettin, R. Marculescu, D. Marculescu, and P. P. Panda, CASES: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2014.
"The EDA Challenges in the Dark Silicon Era," M. Shafique, S. Garg, D. Marculescu, and J. Henkel, DAC: Proceedings of the Design Automation Conference, pp. 6, 2014.
"Beyond Poisson: Modeling Inter-Arrival Times of Requests in a Data," D.-C. Juan, L. Li, H.-K. Peng, D. Marculescu, and C. Faloutsos, PAKDD: Pacific-Asia Conference on Knowledge Discovery and Data Mining, 2014.
"A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis," Z. Qian, D.-C. Juan, P. Bogdan, C.-Y. Tsui, D. Marculescu, and R. Marculescu, ASPDAC: IEEE/ACM Asian-South Pacific Design Automation Conference, 2014.
"Workshops on Extreme Scale Design Automation (ESDA) Challanges and Opportunities for 2025 and Beyond," R.I. Bahar, A. K. Jones, S. Katkoori, P.H. Madden, D. Marculescu, and I. Markov, Computing Community Corsortium (CCC); Magazine, 2014.
"Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip-Multiprocessors," D.-C. Juan, S. Garg, and D. Marculescu, ACM Transactions on Design Automation of Electronic Systems, vol. 19, no. 4, 2014.
"Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment," K.-C. Wu and D. Marculescu, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 1, pp. 136-145, 2014.
"Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment".
Wu, K.-C., & Marculescu, D. (2014). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(1), 136-145.
"Addressing Process Variations at the Microarchitecture and System Level".
Garg, S., & Marculescu, D. (2013). Foundations and Trends in Electronic Design Automation, 6(3), 217-291.
" Learning the Optimal Operating Point for Many-Core Systems with Extended Range Voltage/Frequency Scaling. ".
Juan, D.-C., Garg, S., Park, J., & Marculescu, D. (2013).CODES+ISSS: IEEE/ACM International Conference on Hardware-Software Codesign and System Synthesis, 1-10.